AXI BRAM. Calibration Signals 1. Memory Interleaving is used to improve the access time of the main memory. AMBA AXI Advanced eXtensible Interface AMBA AXI PROTOCOL CONTENTS Key Features Objectives Channel Architecture Basic Transaction Signal Descriptions Addressing Options Channel Handshake AMBA AXI PROTOCOL Key Features • Separate address/ control and data phases • Separate read and write channels to enable low-cost Direct. AXI and AXI lite master. But it's not the only possible source of interleaved write data. An AXI master can provide two write addresses one after another if there is support of two outstanding addresses. #- Configure the AXI3 Slave VIP interleaving depth >1. If the transmission unit is a block or packet. Recently, I read "AMBA AXI Protocol. One major up-dation seen in AXI is that, it includes information on the use of default signaling and discusses the interoperability of components which can’t be. 0 03 June 2011 D-2c Non-Confidential Public beta draft of AMBA AXI and ACE Protocol Specification 28 October 2011 D Non-Confidential First release of AMBA AXI and ACE Protocol Specificationaxi report - Download as adenine PDF press view online for cost-free. The write data interleaving depth is the number of addresses for which a slave can accept interleaved data. In a write transaction, the slave uses the write response channel to signal the completion of the transfer to the master. The master sends the last data item, the WLAST signal. 2. Azad Mishra Tracking. AXI4 carries QoS, AXI3 does NOT suppor QoS. Synopsys NO supporting write interlock in AXI3. request regardless if the request was a write or a read. Help me to understand the reasoning behind the following ordering rule imposed by AXI protocol for write data interleaving. There is one write strobe for each eight bits of the write data bus, therefore WSTRB [n] corresponds to. to SRAM memory slave. インターリーブまたはインターリービング（英: Interleaving）は計算機科学と電気通信において、データを何らかの領域（空間、時間、周波数など）で不連続な形で配置し、性能を向上させる技法を指す。Multiple streams of data can be transferred (even with interleaving) across a master and slave. The DDRMC is a dual channel design with fine interleaving disabled. The WSTRB [n:0] signals when HIGH, specify the byte lanes of the data bus that contain valid information. Wait states are used if the buffer is full, or has less than 128 bytes of available space. A locked transaction is changed to a non-locked transaction and propagated by the MI. v : AXI nonblocking crossbar interconnect rtl/axi. Interleaving allows you to send WID transfers for a number of outstanding AW transfers, BUT. FIG. here is the part axi slave rtl generated by vivado. I have and watch many IP providers e. Why streaming support,it’s advantages? Write an assertion on handshake signals ready and valid, ready comes after 5 cycles from the start of valid. Power Attorney Livre Cri Was Of Use. axi_ram_wr_rd_if module. 16. axi_extra_0_0_wuser_data: 32: Input: Extra Write Data (AXI WUSER port). • uses burst-based transactions with only the start address issued. • support for unaligned data transfers, using byte strobes. From AXI4-Stream Interconnect PG035, "the IP core is capable of performing data switching/routing. As per the standards, 4KB is the minm. In the last article, we introduced AXI, the Advanced Extensible Interface, part of the ARM AMBA specification for SoC design. 1 in the current AXI protocol spec for details of this. 133. 4. 3. -Joe G. awaddr { Write address, the write address bus gives the address of the transaction. By interleaving the two write data streams, the interconnect can improve system performance. axi_extra_0_0_wuser_strb: 4: Input. p. {"payload":{"allShortcutsEnabled":false,"fileTree":{"AXI_Protocol/Design and Verification":{"items":[{"name":"AXI_Interface. and interleaved read data completion of the transactions. The software would keep writing over the data in DRAM until a. 如图所示，slave在返回了一个RID为ID2. The new() function has two arguments as string name and uvm_component parent. AXI RAM write interface with parametrizable data and address interface widths. 1 88PG059 December 20, 2017 Chapter 3: Designing with the Core. erification of a. As per the standards, 4KB is the minm. This site uses cookies to store information on your computer. AXI3 supports barred transfers, AXI4 does NOT support locked transfers 4. 1 in the current AXI protocol spec for details of this. Let’s call the two queues ref_q for Reference transactions and dut_q for DUT transactions. Data interleaving, however, is not supported. {"payload":{"allShortcutsEnabled":false,"fileTree":{"drivers/dma":{"items":[{"name":"bestcomm","path":"drivers/dma/bestcomm","contentType":"directory"},{"name":"dw. I change the hardware in EDK and then run the memory writing code in SDK and check if the data I write is being written to memory with delay or not. g. the data interleaving is responsible for slaves and the write data interleaving is responsible for masters. These features enable the implementation of high-performance interconnect, maximising data throughput and system efficiency. Interleaving allows you to send WID transfers for a number of outstanding AW transfers, BUT. Firstly, I took DUT for testing purposes which is a UART module with AXI-Stream user interface. No. 0 03 June 2011 D-2c Non-Confidential Public beta draft of AMBA AXI and ACE Protocol Specification 28 October 2011 D Non-Confidential First release of AMBA AXI and ACE Protocol SpecificationAXI4 Cross-bar Interconnect ¶. Adds test_i port for DFT. The BREADY can be low before the assertion of BVALID. Initialization of the AXI Slave VIP Memory Model write data via a backdoor memory write. 1. Strobing is one of the main features of AXI, mainly involved during its write burst. Typical Use Case for AXI DMA and AXI4 Ethernet. Since AXI has 5 parallel channels running, many wires are used to lay the layout. From the AMBA AXI4-Stream specification , the TDEST signal can be used to route AXI4 data stream. 8. pdf". A rather significant change seems to be the banning of write interleaving, which could help improve the system throughput. AXI3 helps locked transfers, AXI4 does NOT support locked transfers. And as section A5. Enables sharing the PCIe AXI DMA module between multiple request sources, interleaving requests and distributing responses. 1 Answer. Everything runs fine, the Linux application can start the VDHL AXI master to. HPS Stops on the First Read Request to SDRAM 2. DUT has both Tx and Rx instansiated inside which means user can repalce any of these two with user specific Tx or Rx if they are compatible. By continuing to use our site, you consent to our cookies. A company shall be a Subsidiary only for the period during which such control Subject to the provisions of Clauses 2, 3 and 4, ARM hereby grants to LICENSEE a perpetual, non-exclusive, non-transferable, royalty free, worldwide licence to:(i) use and copy the relevant AMBA Specification for the purpose of developing and having developed products. value on the address channel. 5. The base addresses for slaves in the interconnect are also hence assigned in multiples of 4K. 0 03 June 2011 D-2c Non-Confidential Public beta draft of AMBA AXI and ACE Protocol Specification 28 October 2011 D Non-Confidential First release of AMBA AXI and ACE Protocol SpecificationAXI4 Cross-bar Interconnect ¶. AXI uses well defined master and slave interfaces that communicate via. • AXI Protocol Converter connects one AXI4, AXI3 or AXI4-Lite master to one AXI slave of a different AXI memory-mapped protocol. Gaming, Graphics, and VR. Handles bursts and presents a simplified internal memory interface. The reordering depth of a slave is the slave's ability to process multiple transactions (using different IDs) at the same time, so that possibly a later started transaction could actually complete before earlier started transactions. You can initiate an AXI write transaction by issuing a valid Write Address signal on the AXI Write Address Bus, AWADDR. . Stage 2: Write Calibration Part One 1. mulation and. 而out-of-order和interleaving则是相对于 transaction，out-of-order说的是发送transaction 和接收的cmd之间的顺序没有关系，如先接到A的cmd，再接到B的cmd，则可以先发B的data，再发A的data. b). Interleaving memories, additional memories, wider data widths, and running the memories faster are options to consider. find likely ancestor, descendant, or conflicting patches for. The problem is with your combination of the write address and the write strobes. AXI Channels Read transactions are handled similar to write transactions, except that before transferring the transaction to the AXI4 master read channel, the PCIESS checks the transmit buffer for available space. • separate read and write data channels, that can provide low-cost Direct Memory Access (DMA)The purpose of this page is to describe the the Xilinx Framebuffer Write / Read DMA driver. With the Rambus CXL 2. Pipelined AXI driver; back to back transfers with 0 in-between wait clocks. In the past when writing to DDR ram that is connected to the PS, I have used Xilinx AXI DMA to DMA data into the PS. Hi, I am trying to use DDR4 SDRAM ( MIG 2. Allows reads to bypass writes, in contrast to axi_to_mem, however needs more hardware. 19 March 2004 B Non-Confidential First release of AXI specification v1. svt_axi_port_configuration:: perf_min_write_bandwidth = -1. 4. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect. 1 Solution. Figure 2-19: AXI Reference Guide UG761 (v13. For bulk memorytomemory transfers, we have developed a custom lowlatency multiPipelined AXI driver; back to back transfers with 0 in-between wait clocks. • uses burst-based transactions with only the start address issued. In VU+ HBM, there is a hardened AXI Switch which enables access from any of the 32 AXI channels to any of. The higher bits can be used to obtain data from the module. In AXI4 we don't have write data interleaving, so if your master is issuing multiple write transactions using different. Apr 23, 2014. This approach makes good use of memory. sv contains all dut parameters; A master driver - acts as an AXI master; A slave driver - acts as an AXI slave; Coverage collector; Scoreboard (counts address packets and response packets) Good whitepaper on slave sequences:19 March 2004 B Non-Confidential First release of AXI specification v1. sv","path":"src/axi_atop_filter. In this work, single master and single slave communication using AXI protocol with 32-bit SARM are designed. The controller handles all the command, address, and data sequences, manages all the hardware protocols, and allows access NAND flash memory simply by reading or writing into the operational registers. AMBA AXI and ACE Protocol Specification Version E. p. write(0x0000, b'test') data = await axi_master. State For Research Reference For And Mission Kirkland. Figure 1. Is it . Axi handshake. ME have seen many IP providers e. I am pretty new to AMBA protocol and I am specifically interested in AXI-4. In AXI4 we don't have write data interleaving, so if your master is issuing multiple write transactions using different. -Joe G. Then the data for this address is transmitted Master to the Slave on the Write data channel. Following is my write channel code : // // File name: axi_mcb_w_channel. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. I was going through write data interleaving section in ARM AXI3 protocol. Enabling the Debug Report x. For this the highest bits of the aw_id get pushed into a FIFO. One master port will interface with AXI slave interface. Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec. It addresses high-bandwidth, high-clock-frequency system designs and includes features that make it suitable for high-speed interconnect, typical in mobile and consumer applications. Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving: Multiple Read commands can be executed simultaneously and data interleaving is supported as long as all condition for ordering are followed. Customize the PS to enable the AXI HP0 and AXI HP2 interface: Right-click the ZYNQ7 Processing System core and select Customize Block. By this feature, write data can be issued in advance to its address. AXI3 supports write interleaving. The objectives of the latest generation AMBA interface are to: be suitable for high-bandwidth and low-latency designs. FIG. 1,298. Arm* Cortex*-A53 MPCore* and CoreSight* Errata x. I have including seen many IP providers e. dfi-axi ddr4 m. when the WID is present in the old AXI version, a WDATA re-order mechanism will be inferred, and thanks to the remove of WID, we do not need that mechanism any longer. A. Parameters axi_req_t: type. AXI3 supports write interleaving. Hi Folks, We need a clarification on Read Data Interleaf on AXI4 Readers Data Interleaving is endorsed on AXI4 additionally following will my understanding on Data Interleaving AXI4 - read data interleaving - Embedded forum - Support forums - Arm Community / Out-of-order execution - WikipediaAXI Interconnect Product Guide v2. • Supports simultaneous read and write operations from AXI to PLB. Your write addresses are 1,2,3. Re-ordering implies the transactions complete in a different order to that the AR channel transfers were completed, whereas interleaving suggests that more that one read data stream can be active, so data in successive transfers could be for different transactions. the data interleaving is responsible for slaves and the write data interleaving is responsible for masters. (There was some connection problem. wstrb { Write strobes, his signal indicates which byte lanes to update in memory3 While AXI4 props burst lengths of up the 256 beats. Note: The AXI Interconnect core is intended forWrite interleaving; this feature was retracted by AXI4 protocol. Versal Adaptive SoC CCIX-PCIe Module (CPM) Root port Linux driver. Integrated Memory Controller . although me have twos questions info AXI according° Write interleaving. AXI3 helps locked transfers, AXI4 does NOT support locked transfers. AXI3 supports locked transfers, AXI4 does NO assist locked transfers 4. vinash. And as section A5. then the BFM attempts to perform write data interleaving. Activity points. interleaving. PCIe AXI master module. AXI interconnect performs Clock crossing and Data width conversion and connects to DDR4 MIG on the Master Side. I am currently in the process of moving from an AXI interface to a segmented memory interface to increase the throughput over the PCIe link as the current AXI-based. Verification IP (VIP) supports all four types of atomic transactions:. 17. Example 1. However, the word of the data interleaving is not included in. Wrapper for pcie_us_axi_dma_rd and. However, a master interface can interleave write data with different WID values if the slave interface has a write data. The NAND DMA controller accesses system memory using its AXI master interface. By disabling cookies, some features of the site will not workWrite interleaving with Multi-AXI master Hi, I have multiple questions related to multi-master AXI4 system. v under the block design in the sources window . Interleaving simply means breaking a single transmission unit up into smaller pieces, and spreading those pieces out in time by sequencing them with pieces from other transmission units. The master can assert the AWVALID signal only when it drives valid address. If a slave does not support write data interleaving (see Write data interleaving on page 8-6), the master must issue the data of write transactions in the same order in which it issues the transaction addresses. What is the difference between burst and beat? A ‘beat’ is an individual data transfer within an AXI burst. 17. X12039. AXI has the ability to issue multiple outstanding addresses and out-oforder transaction completion, but AXI has the ability of removal of locked transactions and write interleaving. Multiple Intellectual Property (IPs) are integrated in a single SoC and these IPs communicate with the help of various bus protocols. 19 March 2004 B Non-Confidential First release of AXI specification v1. 0 03 June 2011 D-2c Non-Confidential Public beta draft of AMBA AXI and ACE Protocol Specification 28 October 2011 D Non-Confidential First release of AMBA AXI and ACE Protocol Specificationawait axi_master. Write transaction ID on the GIF is verified for write ID consistency between the AXI and the GIF without write interleaving or out-of-order write responses. This document gives explanation about Cortex-A9 AXI masters. +1 Colin Campbell over 4 years ago. AXI enables out-of-order transaction completion and the issuing of multiple outstanding addresses. 1] AXI is a multi-channel bus with 5 independent channels like Write address channel, Read address channel, Write data channel, Read data channel, Write response channel (Read Response is sent. The Figure 2. g. Configurable write and read interleave depth. 0 AXI. >In case if we have 2 burst transfers with A (awid=0,wlen=2), B (awid=1,wlen=2) then this can be interleaved as following Let's assume that A is issued first. 2 states, if you have an AXI3 legacy deisgn which needs a WID. Memory Interleaving is less or More an Abstraction technique. v. Working of DMA Controller. The AMBA AXI protocol supports high-performance, high-frequency system designs. However, since L2CC masterFree essays, homework help, flashcards, research papers, book reports, term papers, history, science, politicsStage 1: Read Calibration Part One—DQS Enable Calibration and DQ/DQS Centering 1. 19 March 2004 B Non-Confidential First release of AXI specification v1. What is the AXI capability of data interleaving? Explain outoforder transaction support on AXI? Explain multiple outstanding address pending?Module axi_to_mem_interleaved. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one. I'm a graduation student lives in south Korea. axi_fifo: Inserts a FIFO into all 5 AXI4 channels; add module and its testbench; axi_test: Add mapped mode to the random classes as well as additional functionality to the scoreboard class. 1A, the data transmitted by the AXI masters through an NoC router are transferred to an AXI slave 30 through an NI 20. The transfer will be split into one or more bursts according to the AXI specification. Stage 3: Write Calibration Part Two—DQ/DQS Centering 1. ° Write interleaving: This feature was retracted by AXI4 protocol. AXI3 supports locked transfers, AXI4 does NOT support locked transfers 4. The solution requires two queues (of the same type) and a search-and-compare method. We could not find that page in version E or the latest version, so we have taken you to the first page of version E of AMBA AXI Protocol Specification. #- Configure the AXI3 Slave VIP interleaving depth >1. This approach makes good use of memory. PCIe AXI DMA module for Xilinx Ultrascale series FPGAs. TheReaction score. AXI4 supports QoS, AXI3 does NOT support QoS. If two or four instances of the MC are selected, they are configured to form a single interleaved memory. Why is the CONNECT method bottom up in UVM? But the reason for being bottom up approach may be because of port export connection in the graph which extends from lower level to high level components and after which connect method can be called which extends from uvm_port_base#IF. 1) I would like to know how read and write address requests issued to slave are associated with read or write data. While AXI4 supports burst lengths of up to 256 beats. The AVI Mux filter takes the video stream from the capture pin and packages it into an AVI stream. Hi, I am trying to use DDR4 SDRAM ( MIG 2. . 0 AXI. • Write data interleaving and write data Out-of-Order • Transaction with same ARID value to different slaves • Low-power interface of the AXI busStrobing is one of the main features of AXI, mainly involved during its write burst. CT-macros allowing to instantiate AXI structs with custom channel type names. 2 of the AXI Spec (ARM document IHI 0022F. But it's not the only possible source of interleaved write data. The first 1, 2 and 3 byte strobes must be zero because you address is skipping those. when i have two questions aboutThis site uses cookies to store information on your computer. Read now: data analyst course in hyderabad. Output (MI) SIZE = si. The build phase is top down because the parent component's build_phase constructs the child. Transaction address will be randomly selected based on system address map. sv. The AMBA 4 specifications introduced more interface protocols on top of the AMBA 3 specifications, including ACE, the AXI Coherency Extensions. i understood that read transactions enable interleaving. 1) March 7, 2011. Download it for free and explore the challenges and solutions of data sharing. Help me to understand the reasoning behind the following ordering rule imposed by AXI protocol for write data interleaving. This document gives explanation about Cortex-A9 AXI masters. A single instance of the AXI NoC IP can be configured to include one, two, or four instances of the integrated MC. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. d. AXI BFM. AXI3 sustains closed transfers, AXI4 does NO support locked transfers 4. . Polymorphic interface; params_pkg. This paper presents a work aimed to design the AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are. It performs the following steps: Initialization and configuration of the AXI Verification IPs. WID is removed in AXI4, so WDATA must strictly follow the AW order. WID is removed in AXI4, so WDATA must strictly follow the AW order. The Write data interleaving of AXI protocol specification says: "A master interface that is capable of generating write data with only one AWID value generates all write data in. ° Configurable Write and Read transaction acceptance limits for each connected master. v : AXI central DMA engine rtl/axi_cdma_desc_mux. Synopsys supporting burst lengths up to 256 beats in AXI3Write data and read data interleaving support. I'm a graduate student living in south Korea. g. Features of AXI 5 Channels (Write address, Write data, Write Response, Read data/response, Read address ) No strict timing relationship between address and data signal On chip, Point to Point Communication protocol Multiple Outstanding(Multiple request) Burst based transactions with only start address issued Aligned and non-aligned address support Out of order Data interleaving Atomicity. AXI3 supports write interleaving. 0 03 March 2010 C Non-Confidential First release of AXI specification v2. It is a widely implemented Practice in the Computational field. 1) A1 A2 B1 B2 (In-order)-> This is legal. and sending the subsequent transaction. AXI3 masters must be configured as if connected to a slave with Write interleaving depth of one. 2. Synopsys NO supporting write interlock in AXI3. Documentation and usage examples. Performance constraint on the minimum expected bandwidth for write transfers in a given time interval. v. AXI3 supports note interleaving. Update the following part around lines. Resources Developer Site; Xilinx Wiki; Xilinx GithubSo for using this module it is recommended to extend each AXI ID by the required amount of bits indicating the index of the respective slave port, before being sent over this module. Word count register – It contains the. AXI4 supports QoS, AXI3 does NOT suppor QoS. In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) at axi slave model, then the data can be sent as following. 8. Develop and analyze applications with graphics and gaming tools, guides, and training for games developers. Writing a Predefined Data Pattern to SDRAM in the Preloader. 14 AXI Reference Guide UG761 (v13. Develop and analyze applications with graphics and gaming tools, guides, and training for games developers. Bufferable AXI. sequence_length 1. By disabling cookies, some features of the site will. AXI read and write data channels by introducing. WID is needed to support write data interleaving described in AXI3, but this isn't supported in AXI4, so no requirement to have a WID signal. This site uses cookies to store information on your computer. Tune for performance and re-simulate: Ensure that you have the right number of NoC NMUs and DDRMCs to meet your requirements. The configurations where aliasing occurs have the following conditions: 1. Write-Write-Write-Write or Write-Read-Write-Read, etc. While AXI 4 only supports read data interleave. [Chapter 8. The following 5×5 torus is 3-interleaved with 6 colors. For example, if the transmission unit is a byte or word, you might interleave its bits with several other words. 2). • AXI Data FIFO connects one AXI memory-mapped ma ster to one AXI memory-mapped svt_axi_port_configuration:: perf_min_write_bandwidth = -1. The problem was that there was no awready on AXI interface at the VIP. Inside Top module. txt) or read online for free. •. 4. 4. 0 03 June 2011 D-2c Non-Confidential Public beta draft of AMBA AXI and ACE Protocol Specification 28 October 2011 D Non-Confidential First release of AMBA AXI and ACE Protocol Specificationemploying the Advanced extensible Interface (AXI) proto col and an interleaving method thereof, and more particu larly, to an NoC system employing the AXI protocol and an interleaving method thereof, capable of Smoothly transmit ting data according to the interleaving acceptance capability of an Intellectual Property (IP) when the AXI protocol isAXI3 write interleaving is not supported and should not be used with Xilinx IP. g. 4) is the case of the interleave but AXI4 does not permit the write interleaving. awvalid { Write address valid, indicates that valid write address and control information are available. Documentation and usage examples. A rather significant change seems to be the banning of write interleaving, which could help improve the system throughput. ridge. Appendix A Comparison with the AXI4 Write Data. axi_throttle: Add a module that limits the maximum number of outstanding transfers sent to the downstream logic. . There is no write data interleaving in AXI4. See the tests directory, verilog-axi, and verilog-axis for complete testbenches using these modules. v. For a write transaction the W beats belonging to an AW request have to be sent in order. sv","path":"AXI_Protocol/Design and. 是否支持读交织只与slave的设计有关。. The problem I am facing is in AXI interface of MIG where 4-bit ID signal is present for all the transactiPlease answer. The figures below are taken from our VCU128 HBM Performance and Latency demo and attempt to highlight the bandwidth/throughput results from several different AXI Switch configurations. The user logic should provide a valid write address in the. I was going through write data interleaving section in ARM AXI3 protocol. Hi I am using Vivado 2017. Tell. . 0 03 March 2010 C Non-Confidential First release of AXI specification v2. This book is for AMBA AXI Protocol Specification. Learn about cache coherency in Arm systems with this comprehensive white paper. 0 03 June 2011 D-2c Non-Confidential Public beta draft of AMBA AXI and ACE Protocol Specification 28 October 2011 D Non-Confidential First release of AMBA AXI and ACE Protocol SpecificationAn interleaving method for a Network-on-Chip (NoC) system employing an Advanced eXtensible Interface (AXI) protocol, the interleaving method comprising: storing data transmitted from a plurality of AXI Intellectual Properties (IPs) by classifying the data according to the plurality of AXI IPs;Balanced interleavingで用いたランキングAとBの例の場合、Team draft interleavingでも全く同じ結合ランキングが得られます（ただし、チーム割当まで考慮すると、Balanced interleavingとは異なり、4種類のランキングが生成される（後述））。There is one write strobe bit for every eight bits of write data. • Support for Read-only and Write-only masters and slaves, resulting in reduced resource. Ordering Model. 3. com - online owner manuals libraryLoading Application. AXI3 supports write interleaving. 5. 14. Write Data Interleaving in AXI3 Slaves: With Write Data Interleaving, an AXI3 slave can accept interleaved write-data with different AWID values. Then when reading back, each successive pixel comes from a new bank allowing some interleaving of row activation and readout. Write interleaving is hardly used by regular masters but can be used by fabrics that. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one.